One type of HEMT using an InP substrate adopts the structure that a buffer layer, a channel (electron transit) layer and a carrier (electron) supply layer are subsequently epitaxially grown, thereafter a contact cap layer is grown, the cap layer under the gate electrode is removed, and a T-shaped gate electrode is formed on the carrier supply layer. It is desired to form an insulating film on the surface of a compound semiconductor layer in order to maintain tight adhesion between the surface of the compound semiconductor layer and a resist layer during a wet etching process.
JP-A-HEI-6-232179 discloses the method and structure that an insulating layer is stacked on a cap layer, an opening is formed through the insulating layer, the cap layer is wet etched from the opening, and a gate electrode is formed through the opening. The method and structure will be described with reference to FIGS. 6A to 6E.
The structure shown in FIG. 6A is formed by manufacture processes shown in FIGS. 6B to 6E.
As shown in FIG. 6B, by molecular beam epitaxy (MBE) or organic metal vapor phase epitaxy (OMVPE), a buffer layer 111 of InAlAs lattice matching non-doped InP or InP and having a thickness of about 300 nm is grown on a semi-insulating (si) InP substrate 110, a channel layer 112 of InGaAs having a thickness of about 15 nm is grown on the buffer layer 111, an electron supply layer 113 of In0.52Al0.48As having an electron concentration of 5×1018 cm3 and a thickness of 40 nm is grown on the channel layer 112, and a cap layer 114 of In0.53Ga0.47As having an electron concentration of 5×1018 cm3 and having a thickness of 10 nm is grown on the electron supply layer 113. The channel layer 112 may be made of InP.
As shown in FIG. 6C, ohmic electrodes 115 and 116 for drain/source regions are formed on the cap layer 114 in predetermined areas by vapor deposition, and high concentration n-type layers are formed under the ohmic electrodes 115 and 116 by an alloying process. Next, an SiN insulating film 117 of about 50 to 100 nm is formed by plasma CVD. Insulating material such as SiO2 and SiON may be used which can be formed at a lower temperature than SiN.
As shown in FIG. 6D, a photoresist film FA having an opening is formed by photolithography, and the insulating film 117 is etched by using the photoresist film FA as an etching mask to form an opening A1. The insulating film 117 formed with the opening A1 is used as a mask when performing recess etching to be described later, and defines a channel length and width of the gate electrode. After the opening A1 is formed, the photoresist film FA is removed.
As shown in FIG. 6E, by photolithography, a photoresist film FB is formed having an opening which is inclusive of the opening A1 and has an area B1 broader than that of the opening A1. After the photoresist film FB is formed, the cap layer 114 is recess-etched by using the insulating film 117 as a mask to form a recess broader than the opening A1 of the insulating film 117 through the cap layer 114. This recess etching may use etchant of phosphoric acid aqueous solution and hydrogen peroxide aqueous solution. A recess structure is formed also in the electron supply layer 113.
Next, Ti/Pt/Au are sequentially formed by vacuum deposition at thicknesses of 50 nm, 50 nm and 500 nm, respectively, and an unnecessary photoresist FB is removed by lift-off to leave a T-shaped gate electrode.
In this manner, the Schottky gate electrode 118 shown in FIG. 6A is formed. A leg portion of the Schottky gate electrode 118 is formed in a rectangular shape along the opening A1 of the insulating film 117, and although the Schottky gate electrode contacts the electron supply layer 113, it does not contact the cap layer 114. The opening A1 is hermetically sealed with the Schottky gate electrode 118, and the inner space formed in the recess structure is completely shut off from an external atmosphere.
According to the structure and manufacture method shown in FIGS. 6A to 6E, the mask used for the recess etching restricts the layout of the gate electrode, and the gate electrode cannot be positioned nearer to the side wall of the cap layer than the opening position of the SiN film. Since the recess structure is symmetrical to the gate electrode, a drain offset structure cannot be realized in which the gate electrode is set nearer to the source electrode and remoter from the drain electrode to lower a source resistance.
International Publication WO 03/067764 proposes to realize the drain offset structure in the following manner. A dummy pattern of phosphosilicate glass (PSG) or the like is formed on a cap layer, an SiN layer is deposited on the dummy pattern, and an opening reaching the cap layer is formed through the SiN film at the position asymmetrical to source/drain regions at which a gate electrode is desired to be formed, to etch and remove the dummy pattern via the opening. The cap layer exposed in the area where the dummy pattern was removed is etched via the opening to realize the drain offset structure.
Similar points to JP-A-HEI-6-232179 are that the SiN film in an eaves shape exists above the cap layer and the gate electrode contacts the SiN film. Although the drain offset structure can be realized, the layout of the gate electrode is restricted by the eaves structure of the SiN film, and a parasitic capacitance exists between the gate electrode and the SiN film in the eaves shape.
The development of compound semiconductor devices using GaN or GaN-containing compound semiconductor is very active. GaN has a high band gap of 3.4 eV, allowing high voltage operations. Since GaN is resistant against high voltage, it is expected to be applied to usage requiring high voltage and high speed operations such as high electron mobility transistors (HEMT) for base stations of mobile phones. There are various reports on GaN-HEMT in which GaN/AlGaN is formed on a substrate of sapphire, SiC, GaN, Si or the like by crystal growth and the GaN layer is used as an electron transit layer. A recent report indicates a breakdown voltage in excess of 300 V in a current-off state. The best output characteristics are obtained by GaN-HEMT using an SiC substrate. A high thermal conductivity of SiC constitutes the best output characteristics. In order to manufacture a high speed operation GaN device, a semi-insulating SiC substrate is used to restrict parasitic capacitance.